The present invention relates to a process for the production of an inverted structure, active matrix display screen. Its preferred use is in the production of liquid crystal flat-faced screens. However, it can also be applied to materials other than liquid crystals, such as electroluminescent, electrochromic, electrolytic and similar materials.
Among the most interesting known processes for producing an active matrix display screen is the so-called two masking level process, as described in French patent application FR-A-2 533 072. In such a process on a transparent wall are produced columns and a matrix of blocks defining the future pixels. Deposition takes place of a stack of three layers, namely of amorphous hydrogenated silicon, insulant and conductor and said stack is etched with rows overlapping the columns and blocks. Therefore a transistor is formed at each overlap with, as the gate the conductive part of the row, as the drain the block and as the source the column. Thus, the gate is placed above the structure, in a so-called "normal" configuration.
The article by Yutaka Miya et al entitled "Two-Mask Step-Inverted Staggered a-Si TFT-Addressed LCDs" published in SID (Society for InformatIon Display) 89 Digest, pp. 155 to 158 describes another process, which also has two masking levels, but which leads to an inverted or reversed structure compared with the structure described hereinbefore, i.e. with a gate positioned at the bottom of the stack of layers. The main stages of this process are illustrated in FIG. 1. On a glass support 1 is deposited a conductive layer, e.g. of chromium, which is etched in the form of parallel rows 2 (part A). This is followed by the deposition of a silicon nitride layer 3, an intrinsic amorphous silicon layer 4 and a doped amorphous silicon layer 5. These layers can be deposited by PECVD (Plasma Enhanced Chemical Vapour Deposition). A positive photoresist 6 is then deposited and the assembly is subject to ultraviolet irradiation through the glass substrate (part B). ln this irradiation operation, the conductive lines or rows constitute an opaque mask so that after development photoresist 7 is only left above the rows 2. These photoresist rows or lines 7 are used as a mask for etching the doped amorphous silicon layer 5 and the intrinsic amorphous silicon layer 4 (part C).
This is followed by the deposition thereon of a conductive layer 8 etched in order to form the columns and blocks which overlap the rows 2 (part D--the representation being diagrammatic). Taking these elements as the mask, the doped amorphous silicon layer 5 is etched in order to reach the intrinsic amorphous silicon layer 4, which completes the transistors. The latter have for the gate G the part of the row 2 located beneath the structure, for the source S the end of the block and for the drain D part of the column (part E).
This procedure suffers from two disadvantages. Firstly the irradiation takes place through the stack formed by the silicon nitride layer 3, the intrinsic amorphous silicon layer 4 and the doped amorphous silicon layer 5. It is therefore necessary to limit these layers to a very limited thickness in order to avoid an excessive absorption, particularly with respect to the intrinsic amorphous silicon layer 4, which absorbs ultraviolet rays. However, as a result of the thinness of the layer the transistors obtained have only mediocre performance characteristics. The other disadvantage is that the metallic layer for forming the columns and blocks is not deposited on a planar surface (parts C and D of FIG. 1), being instead deposited on a surface having reliefs. This leads to the risk of defects, particularly the cutting off of columns.